1. Field of the Invention
The present invention relates to a resonant switching power source apparatus having an overcurrent protection function, and particularly, to a technique of activating the overcurrent protection function even in a case where an output voltage is below a working voltage.
2. Description of the Related Art
FIG. 1 is a circuit diagram showing a resonant switching power source apparatus according to a related art. The power source apparatus includes a diode bridge circuit DB to rectify an output from an AC power source AC and a smoothing capacitor C to smooth the rectified output and provide DC source power. Between terminals of the capacitor C that supplies the DC source power, there are a first switching element Q1 and second switching element Q2 that are connected in series. The first and second switching elements Q1 and Q2 are, for example, MOSFETs.
Between the source and drain of the second switching element Q2, there are connected a voltage resonant capacitor Crv, a resonant reactor Lri, and a series resonant circuit including a primary winding Np of a transformer T1 and a current resonant capacitor Cri. The resonant reactor Lri may be a leakage inductance of the transformer T1. Between terminals of a second winding Ns of the transformer T1, there is connected a rectifying/smoothing circuit including a diode D1 and a capacitor C1 that are connected in series. The rectifying/smoothing circuit rectifies and smoothes a voltage generated on the secondary winding Ns of the transformer T1. A voltage (terminal voltage of the capacitor C1) provided by the rectifying/smoothing circuit is an output voltage supplied to a load L.
Between terminals of the capacitor C1, there is connected an output voltage detector including a resistor R2, a resistor R3, a shunt regulator SR, and a photocoupler emitter PC1-1. In the output voltage detector, the resistors R2 and R3 divide the output voltage into a divided voltage that is sent to the shunt regulator SR. The shunt regulator SR internally compares the divided voltage with a reference voltage and provides a current representative of a differential voltage (hereinafter referred to as “error voltage”) to the photocoupler emitter PC1-1.
A photocoupler receiver PC1-2 has a first end connected through a resistor R1 to a reference power source Vref (not shown) that is incorporated in a controller 110. A second end of the photocoupler receiver PC1-2 is grounded. The photocoupler receiver PC1-2 generates a voltage Vpc in response to the error voltage detected by and transmitted from the output voltage detector. The voltage Vpc is supplied to a non-inverting input terminal (+) of a comparator Comp1. An inverting input terminal (−) of the comparator Comp1 is connected to a first end of a capacitor Ct. A second end of the capacitor Ct is grounded. The first end of the capacitor Ct is also connected to a first end of a resistor Rt. A second end of the resistor Rt is connected to an output terminal N of a flip-flop FF. An output terminal of the comparator Comp1 is connected to a first input terminal of an AND gate AND1.
The resistor Rt is connected in parallel with a diode D2. An anode of the diode D2 is connected to the first end of the resistor Rt and a cathode of the diode D2 is connected to the second end of the resistor Rt. The output terminal N of the flip-flop FF is connected to a high-side driver 11. An inverting output terminal C of the flip-flop FF is connected to the second switching element Q2. The inverting output terminal C of the flip-flop FF is also connected to an input terminal of a pulse generator 12. An output terminal of the pulse generator 12 is connected to a set terminal S of the flip-flop FF.
Operation of the resonant switching power source apparatus with the above-mentioned configuration will be explained. If the output terminal N of the flip-flop FF is at high level, the capacitor Ct is charged through the resistor Rt and the first switching element Q1 is driven through the high-side driver 11. Namely, the first switching element Q1 turns on. At this time, the inverting output terminal C of the flip-flop FF is at low level to turn off the second switching element Q2. The capacitor Ct is continuously charged, and when a voltage Vct of the capacitor Ct reaches the voltage Vpc of the photocoupler receiver PC1-2, the comparator Comp1 provides a low-level output.
The output of the comparator Comp1 is supplied to the first input terminal of the AND gate AND1. A second input terminal of the AND gate AND1 is connected to an overcurrent detector to be explained later. In a normal state, the second input terminal of the AND gate AND1 receives a high-level signal and the output of the comparator Comp1 is supplied to a reset terminal R (negative logic input) of the flip-flop FF, to reset the flip-flop FF. As a result, the output terminal N of the flip-flop FF becomes low and the inverting output terminal C thereof becomes high.
Switching operation of the first and second switching elements Q1 and Q2 is controlled to have a dead time in which the first and second switching elements Q1 and Q2 are both OFF by a circuit (not shown) that delays ON timing of the elements Q1 and Q2.
When the output terminal N of the flip-flop FF becomes low, the first switching element Q1 turns off and the capacitor Ct is rapidly discharged through the diode D2. As a result, the output of the comparator Comp1 again becomes high. Then, the inverting output terminal C of the flip-flop FF becomes high to turn on the second switching element Q2 and provide the pulse generator 12 with a high-level signal.
In response to the high-level signal, the pulse generator 12 sends, after a predetermined period, a low-level signal to the set terminal S (negative logic input) of the flip-flop FF. As a result, the output terminal N of the flip-flop FF becomes high to again turn on the first switching element Q1 and start charging the capacitor Ct through the resistor Rt. At this time, the inverting output terminal C of the flip-flop FF becomes low to turn off the second switching element Q2.
The above-mentioned operation is repeated with an ON period of the first switching element Q1 being determined according to an error voltage detected by the output voltage detector. The predetermined period generated by the pulse generator 12, i.e., a period starting when the pulse generator 12 receives a high-level signal and ending when the pulse generator 12 sets the flip-flop FF determines an ON period of the second switching element Q2. With these ON periods, the first and second switching elements Q1 and Q2 are alternately turned on and off.
The overcurrent detector includes a capacitor Coc, a resistor Roc, a comparator Comp2, and a reference power source OCP1. An overcurrent protector is served by the AND gate AND1 that resets the flip-flop FF in response to an output from the overcurrent detector, thereby turning off the first switching element Q1.
The capacitor Coc and resistor Roc in the overcurrent detector form a series circuit that is connected in parallel with the current resonant capacitor Cri. A non-inverting input terminal (+) of the comparator Comp2 is connected to the reference power source OCP1 that supplies a reference voltage Vref1. An inverting input terminal (−) of the comparator Comp2 is connected to a connection point between the capacitor Coc and the resistor Roc. An output terminal of the comparator Comp2 is connected to a second input terminal of the AND gate AND1.
A current passes through a path extending along the series resonant circuit having the resonant reactor Lri, the primary winding Np of the transformer T1, and the current resonant capacitor Cri, in which a part of the current passes through the capacitor Coc in a manner of a capacitance ratio of the current resonant capacitor Cri and the capacitor Coc. Accordingly, the resistor Roc generates a voltage corresponding to the current passing through the series resonant circuit.
The voltage generated by the resistor Roc is supplied to the inverting input terminal (−) of the comparator Comp2 and is compared with the reference voltage Vref1 of the reference power source OCP1. An output from the comparator Comp2 is supplied to the second input terminal of the AND gate AND1. The AND gate AND1 provides an AND of the output of the comparator Comp1 and the output of the comparator Comp2 and the comparison result is sent to the reset terminal R of the flip-flop FF.
After the first switching element Q1 is turned on, a current passing through the series resonant circuit may increase so that a voltage generated by the resistor Roc reaches the reference voltage Vref1 generated by the reference power source OCP1. Then, the flip-flop FF is reset to turn off the first switching element Q1. This results in restricting the charging of the current resonant capacitor Cri, to restrict power transmitted to the secondary side. This is the overcurrent protection function that limits power supplied to the load L according to a current passing through the series resonant circuit.
FIG. 2 shows operational waveforms in a steady state of the switching power source apparatus of FIG. 1. FIG. 3 shows operational waveforms in an overload state of the same. In FIGS. 2 and 3, Vds(Q2) is a drain-source voltage of the second switching element Q2, Id(Q1) is a drain current of the first switching element Q1, Id(Q2) is a drain current of the second switching element Q2, and If(D1) is a current passing through the diode D1.
In response to signals generated by the controller 110, the first and second switching elements Q1 and Q2 alternately turn on and off with a dead time of about several hundreds of nanoseconds. During an ON period of the first switching element Q1, the current resonant capacitor Cri is charged through the resonant reactor Lri and the primary winding Np of the transformer T1. During an ON period of the second switching element Q2, excitation energy accumulated in an excitation inductance of the transformer T1 is released.
In the ON period of the second switching element Q2, the primary winding Np of the transformer T1 receives a voltage V(Np) provided by dividing a voltage V(Cri) of the current resonant capacitor Cri by an inductance of the primary winding Np and the resonant reactor Lri. The voltage V(Np) of the primary winding Np is clamped when it reaches a value defined by Vo(np/ns), where np is the number of turns of the primary winding Np, ns is the number of turns of the secondary winding Ns, and Vo is an output voltage. A resonant current generated by the current resonant capacitor Cri and resonant reactor Lri is sent to the secondary side. If the voltage V(Np) of the primary winding Np decreases below the value of Vo(np/ns), no energy is transmitted to the secondary side. Instead, the resonant current passes through the series resonant circuit having the resonant reactor Lri, the primary winding Np of the transformer T1, and the current resonant capacitor Cri.
In a normal state of the resonant switching power source apparatus according to the related art, excitation energy is accumulated in the primary winding Np of the transformer T1 during an ON period of the first switching element Q1, and during an ON period of the second switching element Q2, the accumulated energy is reset when the primary winding Np generates a voltage V(Np) defined by Vo(np/ns). As a result, the excitation current returns to a level that is attained just before the first switching element Q1 is turned on, as indicated with a dotted line in the waveform of a current I(Lri) passing through the resonant reactor Lri.